In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high mobility structures for CMOS applications. Traditionally, the prior art method to implement this has been to grow strained Si layers on thick (on the order of from about 1 to about 5 micrometers) relaxed SiGe buffer layers.
Despite the high channel electron mobilities reported for prior art heterostructures, the use of thick SiGe buffer layers has several noticeable disadvantages associated therewith. First, thick SiGe buffer layers are not typically easy to integrate with existing Si-based CMOS technology. Second, the defect densities, including threading dislocations (TDs) and misfit dislocations, are from about 105 to about 108 defects/cm2 which are still too high for realistic VSLI (very large scale integration) bulk substrate (non-SOI) applications. Thirdly, the nature of the prior art structure precludes selective growth of the SiGe buffer layer so that circuits employing devices with strained Si, unstrained Si and SiGe materials are difficult, and in some instances, nearly impossible to integrate.
In order to produce relaxed SiGe material on a Si substrate, prior art methods typically grow a uniform, graded or stepped, SiGe layer to beyond the metastable critical thickness (i.e., the thickness beyond which dislocations form to relieve stress) and allow misfit dislocations to form, with the associated threading dislocations, through the SiGe buffer layer. Various buffer structures have been used to try to increase the length of the misfit dislocation section in the structures and thereby to decrease the TD density.
Another prior art approach, such as described in U.S. Pat. Nos. 5,461,243 and 5,759,898, both to Ek, et al., provides a structure with a relaxed and reduced defect density semiconductor layer wherein a new strain relief mechanism operates whereby the SiGe buffer layer relaxes while reducing the generation of TDs within the SiGe layer.
A further approach to provide low-defect, substantially relaxed SiGe-on-insulator substrate material is disclosed, for example, in co-pending and co-assigned U.S. patent application Ser. No. 10/055,138, filed Jan. 23, 2002, entitled “Method of Creating High-Quality Relaxed SiGe-On-Insulator for Strained Si CMOS Applications”. In this prior art approach, the relaxed SiGe layer is created using a thermal mixing process.
Despite the numerous advances made in the prior art for fabricating SiGe-on-insulator substrate materials, none of the prior art is capable of providing a method in which the interdependence between the SiGe thickness, the Ge content and the strain relaxation, i.e., in plane lattice parameter, can be decoupled so as to provide a SiGe-on-insulator substrate material containing a relaxed SiGe layer having selected values of thickness, Ge content and strain relaxation. The strain relaxation is related to the in-plane lattice parameter (lattice parameter parallel to the SiGe layer surface) of the relaxed SiGe layer formed in the present invention.